A 4.8mW inductorless CMOS frequency divider-by-4 with more than 60% fractional bandwidth up to 70GHz

Frequency synthesizers at mm-waves would benefit from wide-band low-power dividers with large division factors. This work proposes a divider-by-4 based on clocked differential amplifiers working as dynamic CML latches. The clock modulates both the tail current and the load resistance of the differential pair, allowing a wide locking range. Prototypes, realized in 32nm CMOS, operate between 14GHz and 70GHz demonstrating a fractional bandwidth in excess of 60% in the entire range, 4.8mW of maximum power consumption and 55×18μm 2 occupied area.