A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS

A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS

A 30% frequency tuning range 23.5GHz 32nm SOI-CMOS PLL features an adaptively biased VCO. Adaptive biasing of the VCO lowers the average PLL power consumption from 34mW to 24mW, while keeping the jitter below 1.5° RMS across all frequency bands.

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Bibliographische Detailangaben
Hauptverfasser: Plouchart, J.-O, Ferriss, M., Natarajan, A., Valdes-Garcia, A., Sadhu, B., Rylyakov, A., Parker, B., Beakes, M., Babakani, A., Yaldiz, S., Pileggi, L., Harjani, R., Reynolds, S., Tierno, J. A., Friedman, D.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Current measurement
Frequency measurement
Jitter
Phase locked loops
Phase noise
Voltage-controlled oscillators
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Beschreibung
Zusammenfassung:A 30% frequency tuning range 23.5GHz 32nm SOI-CMOS PLL features an adaptively biased VCO. Adaptive biasing of the VCO lowers the average PLL power consumption from 34mW to 24mW, while keeping the jitter below 1.5° RMS across all frequency bands.
ISSN:0886-5930
2152-3630
DOI:10.1109/CICC.2012.6330593