A dedicated image processor exploiting both spatial and instruction-level parallelism

This paper presents the PAPRICA-3 massively parallel SIMD system, designed as a hardware accelerator for real-time image processing tasks. It is composed of a linear array of single-bit processing elements, including a fairly complex pipelined controller, thus allowing the system to take advantage also of the intrinsic parallelism in a program. A programming environment has been developed to ease the prototyping of applications: a code generator converts C++ programs into assembly, and code optimization is performed directly at the assembly level, following a genetic approach. The effectiveness of the processor, as well as of the code optimizer, are discussed with the aid of an application example for handwritten character recognition.