A novel soft error hardened latch design in 90nm CMOS

As a consequence of increasing density and decreasing supply voltage in modern VLSI circuits, gate capacitances and stored charge in sensitive nodes are considerably reduced. This has made sub-100nm CMOS circuits so vulnerable to radiation induced transient faults (TFs). This paper proposes a novel hardened latch design in 90nm CMOS technology. The proposed latch utilizes Schmitt trigger circuits and redundant feedback loops in order to mask transient pulses and harden internal nodes. A creative time redundancy with lower time overhead has been also used to increase circuit reliability. Experimental results reveal that the proposed design is 44% more qualified and has a critical charge (Q crit ) about 3 times higher than an existing Schmitt trigger based hardened latch with an inconsiderable increase in power and performance.