FPGA implementation of LMS self correcting adaptive filter (SCAF) and hardware analysis

The hardware implementation of adaptive filters is a challenging issue in real-time practical noise cancellation, echo cancellation, prediction and system identification applications. In general-purpose applications the hardware utilization and maximum frequency are two important designing criteria. This paper presents hardware implementing of adaptive least mean square (LMS) filter considering fixed step size and self correcting adaptive filter (SCAF) architectures on a spartan3 XC3S400 Field Programmable Gate Arrays (FPGA) chip. The performance of both approaches is compared in terms of convergence speed, hardware utilization and maximum frequency. A CS4334 digital to analog converter (DAC) is considered between FPGA processing board and computer audio card and practical results are monitored by MATLAB SIMULINK using FROM AUDIO DEVICE block.