Design of 0.45V,1.3mW ultra high gain CMOS LNA using gm-boosting and forward body biasing technique

Two fully integrated low noise amplifiers using g m -boosting technique for ultra-low voltage and ultra-low-power GPS applications are designed and simulated in a standard 0.18μm CMOS technology. By employing the folded cascode and forward body bias technique, the proposed LNAs can operate at reduced supply voltage and power consumption. The proposed LNA delivers a power gain (S 21 ) of 17.6 dB with a noise figure of 3 dB, while consuming only 1.1mW dc power with an ultra low supply voltage of 0.45 V. A g m -boosting technique is used to increase the LNA gain and reduce noise figure at the cost of a little circuit power consumption. For the LNA with a g m -boosting technique, a remarkable gain of 20.8 dB gain is achieved with a dc power of 1.3 mW and noise figure 2.9dB. The supply voltage figure of merit(FOM 1 ) and the tuning-range figure of merit(FOM 2 ) are optimal at 46.22 dB/V and 9.61(v.mw) -1 for g m -boosting technique, respectively.