A 2.488-11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications

The paper presents the design of a 2.488 - 11.2 Gbps SerDes transceiver in a 40nm low-leakage CMOS process. The paper explores the architectural and circuit techniques used to meet the stringent requirements of the high-speed SerDes and to mitigate the performance impact of the low-leakage process....

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Vamvakos, S. D., Gauthier, C. R., Rao, Chethan, Canagasaby, K. R., Choudhary, P., Dabral, S., Desai, S., Hassan, M., Hsieh, K. C., Kleveland, B., Mandal, G., Rouse, R., Saraf, R., Wang, A., Yeung, J., Abugharbieh, K., Ying Cao
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Clocks CMOS integrated circuits Decision feedback equalizers Jitter Phase locked loops Receivers Transmitters
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