A 2.488-11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications
The paper presents the design of a 2.488 - 11.2 Gbps SerDes transceiver in a 40nm low-leakage CMOS process. The paper explores the architectural and circuit techniques used to meet the stringent requirements of the high-speed SerDes and to mitigate the performance impact of the low-leakage process....
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Format: | Tagungsbericht |
Sprache: | eng |
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Zusammenfassung: | The paper presents the design of a 2.488 - 11.2 Gbps SerDes transceiver in a 40nm low-leakage CMOS process. The paper explores the architectural and circuit techniques used to meet the stringent requirements of the high-speed SerDes and to mitigate the performance impact of the low-leakage process. The transceiver makes use of a low-jitter LC PLL to enable high-reliability system design. A system modeling approach is also described, which is used for optimizing the architectural trade-offs. The design has 520fs RJ rms and consumes 30.1 mW/Gbps at 11.2 Gbps. |
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ISSN: | 1548-3746 1558-3899 |
DOI: | 10.1109/MWSCAS.2012.6291943 |