A 2.488-11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications
The paper presents the design of a 2.488 - 11.2 Gbps SerDes transceiver in a 40nm low-leakage CMOS process. The paper explores the architectural and circuit techniques used to meet the stringent requirements of the high-speed SerDes and to mitigate the performance impact of the low-leakage process....
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| creator | Vamvakos, S. D. Gauthier, C. R. Rao, Chethan Canagasaby, K. R. Choudhary, P. Dabral, S. Desai, S. Hassan, M. Hsieh, K. C. Kleveland, B. Mandal, G. Rouse, R. Saraf, R. Wang, A. Yeung, J. Abugharbieh, K. Ying Cao |
| description | The paper presents the design of a 2.488 - 11.2 Gbps SerDes transceiver in a 40nm low-leakage CMOS process. The paper explores the architectural and circuit techniques used to meet the stringent requirements of the high-speed SerDes and to mitigate the performance impact of the low-leakage process. The transceiver makes use of a low-jitter LC PLL to enable high-reliability system design. A system modeling approach is also described, which is used for optimizing the architectural trade-offs. The design has 520fs RJ rms and consumes 30.1 mW/Gbps at 11.2 Gbps. |
| doi_str_mv | 10.1109/MWSCAS.2012.6291943 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_6291943</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6291943</ieee_id><sourcerecordid>6291943</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-41f82659c5b7bd90c693f01bc1884727104f247f894d77fbf768ee6fc8042ae03</originalsourceid><addsrcrecordid>eNpF0FtLwzAYxvF4ArfpJ9hNvkC6vEmaw2WprgobE-rhcqRdItG2KW1F_PYqDrx6Ln7wXPwRWgJNAKhZbV_KPCsTRoElkhkwgp-gOQipOEuZMqdoBmmqCdfGnP2DpOe_IH5ACXmJ5uP4RinjCswMPWeYJUJrApAwXFSrEbcfzRRIP8Qp1rHBpRtu3IhDhwXtWtzET9I4-25fHc63uxL7OOD1Q5Fh2_dNqO0UYjdeoQtvm9FdH3eBnta3j_kd2eyK-zzbkAAqnYgAr5lMTZ1WqjoYWkvDPYWqBq2FYgqo8Ewor404KOUrr6R2TvpaU8Gso3yBln-_wTm374fQ2uFrf4zDvwE1n1EN</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A 2.488-11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Vamvakos, S. D. ; Gauthier, C. R. ; Rao, Chethan ; Canagasaby, K. R. ; Choudhary, P. ; Dabral, S. ; Desai, S. ; Hassan, M. ; Hsieh, K. C. ; Kleveland, B. ; Mandal, G. ; Rouse, R. ; Saraf, R. ; Wang, A. ; Yeung, J. ; Abugharbieh, K. ; Ying Cao</creator><creatorcontrib>Vamvakos, S. D. ; Gauthier, C. R. ; Rao, Chethan ; Canagasaby, K. R. ; Choudhary, P. ; Dabral, S. ; Desai, S. ; Hassan, M. ; Hsieh, K. C. ; Kleveland, B. ; Mandal, G. ; Rouse, R. ; Saraf, R. ; Wang, A. ; Yeung, J. ; Abugharbieh, K. ; Ying Cao</creatorcontrib><description>The paper presents the design of a 2.488 - 11.2 Gbps SerDes transceiver in a 40nm low-leakage CMOS process. The paper explores the architectural and circuit techniques used to meet the stringent requirements of the high-speed SerDes and to mitigate the performance impact of the low-leakage process. The transceiver makes use of a low-jitter LC PLL to enable high-reliability system design. A system modeling approach is also described, which is used for optimizing the architectural trade-offs. The design has 520fs RJ rms and consumes 30.1 mW/Gbps at 11.2 Gbps.</description><identifier>ISSN: 1548-3746</identifier><identifier>ISBN: 1467325260</identifier><identifier>ISBN: 9781467325264</identifier><identifier>EISSN: 1558-3899</identifier><identifier>EISBN: 1467325279</identifier><identifier>EISBN: 9781467325257</identifier><identifier>EISBN: 1467325252</identifier><identifier>EISBN: 9781467325271</identifier><identifier>DOI: 10.1109/MWSCAS.2012.6291943</identifier><language>eng</language><publisher>IEEE</publisher><subject>Clocks ; CMOS integrated circuits ; Decision feedback equalizers ; Jitter ; Phase locked loops ; Receivers ; Transmitters</subject><ispartof>2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), 2012, p.5-8</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6291943$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2056,27924,54919</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6291943$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Vamvakos, S. D.</creatorcontrib><creatorcontrib>Gauthier, C. R.</creatorcontrib><creatorcontrib>Rao, Chethan</creatorcontrib><creatorcontrib>Canagasaby, K. R.</creatorcontrib><creatorcontrib>Choudhary, P.</creatorcontrib><creatorcontrib>Dabral, S.</creatorcontrib><creatorcontrib>Desai, S.</creatorcontrib><creatorcontrib>Hassan, M.</creatorcontrib><creatorcontrib>Hsieh, K. C.</creatorcontrib><creatorcontrib>Kleveland, B.</creatorcontrib><creatorcontrib>Mandal, G.</creatorcontrib><creatorcontrib>Rouse, R.</creatorcontrib><creatorcontrib>Saraf, R.</creatorcontrib><creatorcontrib>Wang, A.</creatorcontrib><creatorcontrib>Yeung, J.</creatorcontrib><creatorcontrib>Abugharbieh, K.</creatorcontrib><creatorcontrib>Ying Cao</creatorcontrib><title>A 2.488-11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications</title><title>2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)</title><addtitle>MWSCAS</addtitle><description>The paper presents the design of a 2.488 - 11.2 Gbps SerDes transceiver in a 40nm low-leakage CMOS process. The paper explores the architectural and circuit techniques used to meet the stringent requirements of the high-speed SerDes and to mitigate the performance impact of the low-leakage process. The transceiver makes use of a low-jitter LC PLL to enable high-reliability system design. A system modeling approach is also described, which is used for optimizing the architectural trade-offs. The design has 520fs RJ rms and consumes 30.1 mW/Gbps at 11.2 Gbps.</description><subject>Clocks</subject><subject>CMOS integrated circuits</subject><subject>Decision feedback equalizers</subject><subject>Jitter</subject><subject>Phase locked loops</subject><subject>Receivers</subject><subject>Transmitters</subject><issn>1548-3746</issn><issn>1558-3899</issn><isbn>1467325260</isbn><isbn>9781467325264</isbn><isbn>1467325279</isbn><isbn>9781467325257</isbn><isbn>1467325252</isbn><isbn>9781467325271</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2012</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpF0FtLwzAYxvF4ArfpJ9hNvkC6vEmaw2WprgobE-rhcqRdItG2KW1F_PYqDrx6Ln7wXPwRWgJNAKhZbV_KPCsTRoElkhkwgp-gOQipOEuZMqdoBmmqCdfGnP2DpOe_IH5ACXmJ5uP4RinjCswMPWeYJUJrApAwXFSrEbcfzRRIP8Qp1rHBpRtu3IhDhwXtWtzET9I4-25fHc63uxL7OOD1Q5Fh2_dNqO0UYjdeoQtvm9FdH3eBnta3j_kd2eyK-zzbkAAqnYgAr5lMTZ1WqjoYWkvDPYWqBq2FYgqo8Ewor404KOUrr6R2TvpaU8Gso3yBln-_wTm374fQ2uFrf4zDvwE1n1EN</recordid><startdate>201208</startdate><enddate>201208</enddate><creator>Vamvakos, S. D.</creator><creator>Gauthier, C. R.</creator><creator>Rao, Chethan</creator><creator>Canagasaby, K. R.</creator><creator>Choudhary, P.</creator><creator>Dabral, S.</creator><creator>Desai, S.</creator><creator>Hassan, M.</creator><creator>Hsieh, K. C.</creator><creator>Kleveland, B.</creator><creator>Mandal, G.</creator><creator>Rouse, R.</creator><creator>Saraf, R.</creator><creator>Wang, A.</creator><creator>Yeung, J.</creator><creator>Abugharbieh, K.</creator><creator>Ying Cao</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>201208</creationdate><title>A 2.488-11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications</title><author>Vamvakos, S. D. ; Gauthier, C. R. ; Rao, Chethan ; Canagasaby, K. R. ; Choudhary, P. ; Dabral, S. ; Desai, S. ; Hassan, M. ; Hsieh, K. C. ; Kleveland, B. ; Mandal, G. ; Rouse, R. ; Saraf, R. ; Wang, A. ; Yeung, J. ; Abugharbieh, K. ; Ying Cao</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-41f82659c5b7bd90c693f01bc1884727104f247f894d77fbf768ee6fc8042ae03</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2012</creationdate><topic>Clocks</topic><topic>CMOS integrated circuits</topic><topic>Decision feedback equalizers</topic><topic>Jitter</topic><topic>Phase locked loops</topic><topic>Receivers</topic><topic>Transmitters</topic><toplevel>online_resources</toplevel><creatorcontrib>Vamvakos, S. D.</creatorcontrib><creatorcontrib>Gauthier, C. R.</creatorcontrib><creatorcontrib>Rao, Chethan</creatorcontrib><creatorcontrib>Canagasaby, K. R.</creatorcontrib><creatorcontrib>Choudhary, P.</creatorcontrib><creatorcontrib>Dabral, S.</creatorcontrib><creatorcontrib>Desai, S.</creatorcontrib><creatorcontrib>Hassan, M.</creatorcontrib><creatorcontrib>Hsieh, K. C.</creatorcontrib><creatorcontrib>Kleveland, B.</creatorcontrib><creatorcontrib>Mandal, G.</creatorcontrib><creatorcontrib>Rouse, R.</creatorcontrib><creatorcontrib>Saraf, R.</creatorcontrib><creatorcontrib>Wang, A.</creatorcontrib><creatorcontrib>Yeung, J.</creatorcontrib><creatorcontrib>Abugharbieh, K.</creatorcontrib><creatorcontrib>Ying Cao</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Vamvakos, S. D.</au><au>Gauthier, C. R.</au><au>Rao, Chethan</au><au>Canagasaby, K. R.</au><au>Choudhary, P.</au><au>Dabral, S.</au><au>Desai, S.</au><au>Hassan, M.</au><au>Hsieh, K. C.</au><au>Kleveland, B.</au><au>Mandal, G.</au><au>Rouse, R.</au><au>Saraf, R.</au><au>Wang, A.</au><au>Yeung, J.</au><au>Abugharbieh, K.</au><au>Ying Cao</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A 2.488-11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications</atitle><btitle>2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)</btitle><stitle>MWSCAS</stitle><date>2012-08</date><risdate>2012</risdate><spage>5</spage><epage>8</epage><pages>5-8</pages><issn>1548-3746</issn><eissn>1558-3899</eissn><isbn>1467325260</isbn><isbn>9781467325264</isbn><eisbn>1467325279</eisbn><eisbn>9781467325257</eisbn><eisbn>1467325252</eisbn><eisbn>9781467325271</eisbn><abstract>The paper presents the design of a 2.488 - 11.2 Gbps SerDes transceiver in a 40nm low-leakage CMOS process. The paper explores the architectural and circuit techniques used to meet the stringent requirements of the high-speed SerDes and to mitigate the performance impact of the low-leakage process. The transceiver makes use of a low-jitter LC PLL to enable high-reliability system design. A system modeling approach is also described, which is used for optimizing the architectural trade-offs. The design has 520fs RJ rms and consumes 30.1 mW/Gbps at 11.2 Gbps.</abstract><pub>IEEE</pub><doi>10.1109/MWSCAS.2012.6291943</doi><tpages>4</tpages></addata></record> |
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| identifier | ISSN: 1548-3746 |
| ispartof | 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), 2012, p.5-8 |
| issn | 1548-3746 1558-3899 |
| language | eng |
| recordid | cdi_ieee_primary_6291943 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Clocks CMOS integrated circuits Decision feedback equalizers Jitter Phase locked loops Receivers Transmitters |
| title | A 2.488-11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-12T02%3A30%3A26IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%202.488-11.2%20Gb/s%20multi-protocol%20SerDes%20in%2040nm%20low-leakage%20CMOS%20for%20FPGA%20applications&rft.btitle=2012%20IEEE%2055th%20International%20Midwest%20Symposium%20on%20Circuits%20and%20Systems%20(MWSCAS)&rft.au=Vamvakos,%20S.%20D.&rft.date=2012-08&rft.spage=5&rft.epage=8&rft.pages=5-8&rft.issn=1548-3746&rft.eissn=1558-3899&rft.isbn=1467325260&rft.isbn_list=9781467325264&rft_id=info:doi/10.1109/MWSCAS.2012.6291943&rft_dat=%3Cieee_6IE%3E6291943%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=1467325279&rft.eisbn_list=9781467325257&rft.eisbn_list=1467325252&rft.eisbn_list=9781467325271&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6291943&rfr_iscdi=true |