An architectural power optimization case study using high-level synthesis
Architectural power optimization offers significant power gains in addition to which can be obtained at higher and lower levels of abstraction. Although there has been some academic research for architectural power optimization, the commercial design automation technology is still in infancy and qui...
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creator | Chih-Tung Chen Kucukcakar, K. |
description | Architectural power optimization offers significant power gains in addition to which can be obtained at higher and lower levels of abstraction. Although there has been some academic research for architectural power optimization, the commercial design automation technology is still in infancy and quite behind the current needs of the industry as many portable computing and communication products and greener non-portable products are being introduced into the market. In this paper we describe an environment for exploring low-power architectures using high-level synthesis, which is currently being used for production chip design until comprehensive commercialized alternatives are available. We also present the results and findings from experiments with a CCITT G.721 ADPCM Predictor design, which should benefit on-going research on automated solutions. |
doi_str_mv | 10.1109/ICCD.1997.628922 |
format | Conference Proceeding |
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Although there has been some academic research for architectural power optimization, the commercial design automation technology is still in infancy and quite behind the current needs of the industry as many portable computing and communication products and greener non-portable products are being introduced into the market. In this paper we describe an environment for exploring low-power architectures using high-level synthesis, which is currently being used for production chip design until comprehensive commercialized alternatives are available. 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Although there has been some academic research for architectural power optimization, the commercial design automation technology is still in infancy and quite behind the current needs of the industry as many portable computing and communication products and greener non-portable products are being introduced into the market. In this paper we describe an environment for exploring low-power architectures using high-level synthesis, which is currently being used for production chip design until comprehensive commercialized alternatives are available. We also present the results and findings from experiments with a CCITT G.721 ADPCM Predictor design, which should benefit on-going research on automated solutions.</description><subject>Chip scale packaging</subject><subject>Commercialization</subject><subject>Communication industry</subject><subject>Computer architecture</subject><subject>Computer industry</subject><subject>Design automation</subject><subject>Design optimization</subject><subject>High level synthesis</subject><subject>Portable computers</subject><subject>Production</subject><issn>1063-6404</issn><issn>2576-6996</issn><isbn>9780818682063</isbn><isbn>081868206X</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1997</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotkM1qhDAYRUN_oDJ1X7rKCzhNPk1MloP9Ewa6addDTL6OKY6KiS326StMD1zO7i4OIXecbTln-qGuqsct17rcSlAa4IIkIEqZSa3lJUl1qZjiSipgMr8iCV-VyYIVNyQN4YutFIJroRJS73pqJtv6iDbOk-noOPzgRIcx-pP_NdEPPbUmIA1xdgudg--PtPXHNuvwGzsalj62GHy4JdefpguY_ntDPp6f3qvXbP_2Ule7feY5K2IGANwJVxinFSuYaoS2UmFjeAnCMMx5oxojhAW1Li-haSxDC-ByxRx3-Ybcn389Ih7GyZ_MtBzOHfI_weVPpg</recordid><startdate>1997</startdate><enddate>1997</enddate><creator>Chih-Tung Chen</creator><creator>Kucukcakar, K.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1997</creationdate><title>An architectural power optimization case study using high-level synthesis</title><author>Chih-Tung Chen ; Kucukcakar, K.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i104t-2221d5d4ad980408b59c68eba1725a0e31b8ba55c285c2372bbc0ec22d380d1d3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1997</creationdate><topic>Chip scale packaging</topic><topic>Commercialization</topic><topic>Communication industry</topic><topic>Computer architecture</topic><topic>Computer industry</topic><topic>Design automation</topic><topic>Design optimization</topic><topic>High level synthesis</topic><topic>Portable computers</topic><topic>Production</topic><toplevel>online_resources</toplevel><creatorcontrib>Chih-Tung Chen</creatorcontrib><creatorcontrib>Kucukcakar, K.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chih-Tung Chen</au><au>Kucukcakar, K.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>An architectural power optimization case study using high-level synthesis</atitle><btitle>Proceedings International Conference on Computer Design VLSI in Computers and Processors</btitle><stitle>ICCD</stitle><date>1997</date><risdate>1997</risdate><spage>562</spage><epage>570</epage><pages>562-570</pages><issn>1063-6404</issn><eissn>2576-6996</eissn><isbn>9780818682063</isbn><isbn>081868206X</isbn><abstract>Architectural power optimization offers significant power gains in addition to which can be obtained at higher and lower levels of abstraction. Although there has been some academic research for architectural power optimization, the commercial design automation technology is still in infancy and quite behind the current needs of the industry as many portable computing and communication products and greener non-portable products are being introduced into the market. In this paper we describe an environment for exploring low-power architectures using high-level synthesis, which is currently being used for production chip design until comprehensive commercialized alternatives are available. We also present the results and findings from experiments with a CCITT G.721 ADPCM Predictor design, which should benefit on-going research on automated solutions.</abstract><pub>IEEE</pub><doi>10.1109/ICCD.1997.628922</doi><tpages>9</tpages></addata></record> |
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ispartof | Proceedings International Conference on Computer Design VLSI in Computers and Processors, 1997, p.562-570 |
issn | 1063-6404 2576-6996 |
language | eng |
recordid | cdi_ieee_primary_628922 |
source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Chip scale packaging Commercialization Communication industry Computer architecture Computer industry Design automation Design optimization High level synthesis Portable computers Production |
title | An architectural power optimization case study using high-level synthesis |
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