An architectural power optimization case study using high-level synthesis

Architectural power optimization offers significant power gains in addition to which can be obtained at higher and lower levels of abstraction. Although there has been some academic research for architectural power optimization, the commercial design automation technology is still in infancy and quite behind the current needs of the industry as many portable computing and communication products and greener non-portable products are being introduced into the market. In this paper we describe an environment for exploring low-power architectures using high-level synthesis, which is currently being used for production chip design until comprehensive commercialized alternatives are available. We also present the results and findings from experiments with a CCITT G.721 ADPCM Predictor design, which should benefit on-going research on automated solutions.