VLSI implementation of an eight-state clustering based sequence equalizer
This paper presents the VLSI implementation of a fixed, 8-state CBSE (clustering based sequence equalizer). Simulation results demonstrate superior performance compared to other types of equalizers, such as LTE, DFE and RBF. Furthermore, the architecture presented, does not exhibit performance degra...
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| container_end_page | 1077 vol.2 |
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| creator | Georgoulakis, K. Doumenis, D.G. Aggouras, G. Frantzeskakis, E. |
| description | This paper presents the VLSI implementation of a fixed, 8-state CBSE (clustering based sequence equalizer). Simulation results demonstrate superior performance compared to other types of equalizers, such as LTE, DFE and RBF. Furthermore, the architecture presented, does not exhibit performance degradations due to finite wordlength effects. The design was implemented on FPGA using approximately 24000 gates and it can accommodate transmission rates of up to 8 Mbps. |
| doi_str_mv | 10.1109/ICDSP.1997.628551 |
| format | Conference Proceeding |
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Simulation results demonstrate superior performance compared to other types of equalizers, such as LTE, DFE and RBF. Furthermore, the architecture presented, does not exhibit performance degradations due to finite wordlength effects. The design was implemented on FPGA using approximately 24000 gates and it can accommodate transmission rates of up to 8 Mbps.</description><identifier>ISBN: 0780341376</identifier><identifier>ISBN: 9780780341371</identifier><identifier>DOI: 10.1109/ICDSP.1997.628551</identifier><language>eng</language><publisher>IEEE</publisher><subject>Decision feedback equalizers ; Degradation ; Intersymbol interference ; Least squares approximation ; Maximum likelihood estimation ; Nonlinear distortion ; Receivers ; SAW filters ; Very large scale integration ; Wireless communication</subject><ispartof>Proceedings of 13th International Conference on Digital Signal Processing, 1997, Vol.2, p.1075-1077 vol.2</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/628551$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,4036,4037,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/628551$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Georgoulakis, K.</creatorcontrib><creatorcontrib>Doumenis, D.G.</creatorcontrib><creatorcontrib>Aggouras, G.</creatorcontrib><creatorcontrib>Frantzeskakis, E.</creatorcontrib><title>VLSI implementation of an eight-state clustering based sequence equalizer</title><title>Proceedings of 13th International Conference on Digital Signal Processing</title><addtitle>ICDSP</addtitle><description>This paper presents the VLSI implementation of a fixed, 8-state CBSE (clustering based sequence equalizer). Simulation results demonstrate superior performance compared to other types of equalizers, such as LTE, DFE and RBF. Furthermore, the architecture presented, does not exhibit performance degradations due to finite wordlength effects. The design was implemented on FPGA using approximately 24000 gates and it can accommodate transmission rates of up to 8 Mbps.</description><subject>Decision feedback equalizers</subject><subject>Degradation</subject><subject>Intersymbol interference</subject><subject>Least squares approximation</subject><subject>Maximum likelihood estimation</subject><subject>Nonlinear distortion</subject><subject>Receivers</subject><subject>SAW filters</subject><subject>Very large scale integration</subject><subject>Wireless communication</subject><isbn>0780341376</isbn><isbn>9780780341371</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1997</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNp9jrsOgjAYRpsYE288gE59AbAFymVGjSQOJhhXUvEHa0rBtg769JLo7FlOcr7lQ2hJiUcpSdd5timOHk3T2Iv8hDE6QjMSJyQIaRBHE-QYcycDIWO-T6coPx-KHIu2l9CCstyKTuGuxlxhEM3NumZogCv5NBa0UA2-cANXbODxBFUBHsyleINeoHHNpQHn5zla7banbO8KACh7LVquX-X3VPB3_ACpgTwX</recordid><startdate>1997</startdate><enddate>1997</enddate><creator>Georgoulakis, K.</creator><creator>Doumenis, D.G.</creator><creator>Aggouras, G.</creator><creator>Frantzeskakis, E.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1997</creationdate><title>VLSI implementation of an eight-state clustering based sequence equalizer</title><author>Georgoulakis, K. ; Doumenis, D.G. ; Aggouras, G. ; Frantzeskakis, E.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_6285513</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1997</creationdate><topic>Decision feedback equalizers</topic><topic>Degradation</topic><topic>Intersymbol interference</topic><topic>Least squares approximation</topic><topic>Maximum likelihood estimation</topic><topic>Nonlinear distortion</topic><topic>Receivers</topic><topic>SAW filters</topic><topic>Very large scale integration</topic><topic>Wireless communication</topic><toplevel>online_resources</toplevel><creatorcontrib>Georgoulakis, K.</creatorcontrib><creatorcontrib>Doumenis, D.G.</creatorcontrib><creatorcontrib>Aggouras, G.</creatorcontrib><creatorcontrib>Frantzeskakis, E.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE/IET Electronic Library</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Georgoulakis, K.</au><au>Doumenis, D.G.</au><au>Aggouras, G.</au><au>Frantzeskakis, E.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>VLSI implementation of an eight-state clustering based sequence equalizer</atitle><btitle>Proceedings of 13th International Conference on Digital Signal Processing</btitle><stitle>ICDSP</stitle><date>1997</date><risdate>1997</risdate><volume>2</volume><spage>1075</spage><epage>1077 vol.2</epage><pages>1075-1077 vol.2</pages><isbn>0780341376</isbn><isbn>9780780341371</isbn><abstract>This paper presents the VLSI implementation of a fixed, 8-state CBSE (clustering based sequence equalizer). Simulation results demonstrate superior performance compared to other types of equalizers, such as LTE, DFE and RBF. Furthermore, the architecture presented, does not exhibit performance degradations due to finite wordlength effects. The design was implemented on FPGA using approximately 24000 gates and it can accommodate transmission rates of up to 8 Mbps.</abstract><pub>IEEE</pub><doi>10.1109/ICDSP.1997.628551</doi></addata></record> |
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| identifier | ISBN: 0780341376 |
| ispartof | Proceedings of 13th International Conference on Digital Signal Processing, 1997, Vol.2, p.1075-1077 vol.2 |
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| language | eng |
| recordid | cdi_ieee_primary_628551 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Decision feedback equalizers Degradation Intersymbol interference Least squares approximation Maximum likelihood estimation Nonlinear distortion Receivers SAW filters Very large scale integration Wireless communication |
| title | VLSI implementation of an eight-state clustering based sequence equalizer |
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