Multistack optimization for data-path chip layout

A special multistack structure and optimization technique to partition, place, and wire the data-path macros in the form of the multistack structure are described, taking into account the connectivity of all the chip logic (data path, control logic, chip drivers, on-chip memory). The overall objective is: to fit the circuits within the chip boundary; to ensure data-path internal wirability; as well as external stack wirability to the other circuits; and to minimize wire lengths for wirability and timing. A tool for automatic multistack optimization has been implemented and applied successfully to layout high-density data path chips.< >