A 14 bit self-calibrating charge redistribution SAR ADC

A 14 bit self-calibrating charge redistribution SAR ADC

This paper presents a charge redistribution successive approximation A/D-Converter with 14 bit resolution designed in a 0.35 µm CMOS technology. An enhanced self-calibration technique is applied to correct mismatch of the binary weighted capacitors of a fully differential ADC. In contrast to previou...

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Bibliographische Detailangaben
Hauptverfasser: Haenzsche, Stefan, Henker, Stephan, Schuffny, Rene, Reichel, Thomas, Garzarolli, Matthias
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Accuracy
Arrays
Calibration
Capacitors
CMOS integrated circuits
Production
Switches
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Beschreibung
Zusammenfassung:This paper presents a charge redistribution successive approximation A/D-Converter with 14 bit resolution designed in a 0.35 µm CMOS technology. An enhanced self-calibration technique is applied to correct mismatch of the binary weighted capacitors of a fully differential ADC. In contrast to previous presented solutions, no additional digital calculation is permanently necessary during conversion. Implementation and measurement results prove the concept and show main advantages regarding circuit area, digital complexity and calibration time.
ISSN:0271-4302
2158-1525
DOI:10.1109/ISCAS.2012.6271405