Characterization and modelling of Si-substrate noise induced by RF signal propagating in TSV of 3D-IC stack

TSVs in 3D integrated circuits are a source of noise that can affect nearby transistor performance. So an analytical physics-based model of the TSV-to-substrate coupling is proposed to perform time domain or noise simulations. Silicon measurements at low frequencies and radiofrequencies are reported...

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Hauptverfasser:	Brocard, M., Le Maitre, P., Bermond, C., Bar, P., Anciant, R., Farcy, A., Lacrevaz, T., Leduc, P., Coudrain, P., Hotellier, N., Ben Jamaa, H., Cheramy, S., Sillon, N., Marin, J., Flechet, B.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Capacitance Frequency measurement Integrated circuit modeling Semiconductor device modeling Silicon Substrates Through-silicon vias
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Beschreibung
Zusammenfassung:	TSVs in 3D integrated circuits are a source of noise that can affect nearby transistor performance. So an analytical physics-based model of the TSV-to-substrate coupling is proposed to perform time domain or noise simulations. Silicon measurements at low frequencies and radiofrequencies are reported. Simulations are done using a software performing device and electromagnetic co-simulations. The model and simulations are validated by measurements. Simulations to study the sensitivity of the TSV structure to the layout show changes in the TSV-to-substrate coupling behavior.
ISSN:	0569-5503 2377-5726
DOI:	10.1109/ECTC.2012.6248903