A 71dB dynamic range third-order ΔΣ TDC using charge-pump

A 71dB dynamic range third-order ΔΣ TDC using charge-pump

A high resolution time-to-digital converter (TDC) architecture is proposed. The architecture combines the principles of noise-shaping quantization and charge-pump to build a third-order ΔΣ TDC with a dedicated feedback DAC. Fabricated in a 0.13μm CMOS process, the prototype TDC achieves better than...

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Bibliographische Detailangaben
Hauptverfasser: Gande, M., Maghari, N., Taehwan Oh, Un-Ku Moon
Format: Tagungsbericht
Sprache:eng ; jpn
Schlagworte:
Capacitors
Charge pumps
Delay
Discharges (electric)
Noise shaping
Quantization
Tin
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Beschreibung
Zusammenfassung:A high resolution time-to-digital converter (TDC) architecture is proposed. The architecture combines the principles of noise-shaping quantization and charge-pump to build a third-order ΔΣ TDC with a dedicated feedback DAC. Fabricated in a 0.13μm CMOS process, the prototype TDC achieves better than 71dB DR and 67dB SNDR in 2.81MHz signal bandwidth (OSR=16) and consumes 2.58mW.
ISSN:2158-5601
2158-5636
DOI:10.1109/VLSIC.2012.6243843