A new 3-bit programming algorithm using SLC-to-TLC migration for 8MB/s high performance TLC NAND flash memory

We have developed a new 3-bit programming algorithm of high performance TLC(Triple-level-cell, 3-bit/cell) NAND flash memories for 20nm node and beyond. By using the proposed 3-bit algorithm based on reprogramming with SLC-to-TLC migration, performance and BER is improved by 50% and 68%, respectivel...

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Hauptverfasser:	Seung-Hwan Shin, Dong-Kyo Shim, Jae-Yong Jeong, Oh-Suk Kwon, Sang-Yong Yoon, Myung-Hoon Choi, Tae-Young Kim, Hyun-Wook Park, Hyun-Jun Yoon, Young-Sun Song, Yoon-Hee Choi, Sang-Won Shim, Yang-Lo Ahn, Ki-Tae Park, Jin-Man Han, Kye-Hyun Kyung, Young-Hyun Jun
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Algorithm design and analysis Computer architecture Couplings Flash memory Interference Performance evaluation Random access memory
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Beschreibung
Zusammenfassung:	We have developed a new 3-bit programming algorithm of high performance TLC(Triple-level-cell, 3-bit/cell) NAND flash memories for 20nm node and beyond. By using the proposed 3-bit algorithm based on reprogramming with SLC-to-TLC migration, performance and BER is improved by 50% and 68%, respectively, compared to conventional method. The proposed algorithm is successfully implemented in 21nm 64Gb TLC NAND flash product that provides 8MB/s write and 400MB/s read throughputs.
ISSN:	2158-5601 2158-5636
DOI:	10.1109/VLSIC.2012.6243825