Investigation into the effect of the variation of gate dimensions on program characteristics in 3D NAND flash array

Investigation into the effect of the variation of gate dimensions on program characteristics in 3D NAND flash array

In 3D stacked NAND flash memory, the number of stacked layers tends to increase for high density storage capacity. With the increase of the height of devices, it is important to achieve a good vertical etch profile by which word line (WL) gate dimensions are affected. In this paper, we investigate t...

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Hauptverfasser: Joo Yun Seo, Yoon Kim, Se Hwan Park, Wandong Kim, Do-Bin Kim, Jong-Ho Lee, Hyungcheol Shin, Byung-Gook Park
Format: Tagungsbericht
Sprache:eng
Schlagworte:
3D stacked NAND flash
Arrays
Educational institutions
Flash memory
Logic gates
Microprocessors
Solid modeling
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Beschreibung
Zusammenfassung:In 3D stacked NAND flash memory, the number of stacked layers tends to increase for high density storage capacity. With the increase of the height of devices, it is important to achieve a good vertical etch profile by which word line (WL) gate dimensions are affected. In this paper, we investigate the effect of the variation of gate dimensions on the program characteristics in 3D NAND flash memory array by using TCAD simulation. Also, we compare the cell characteristics of NAND flash with different structures, gate-all-around (GAA) and double gate (DG).
ISSN:2161-4636
2161-4644
DOI:10.1109/SNW.2012.6243320