Demonstration of inter-chip data transmission in a three-dimensional stacked chip fabricated by chip-level TSV integration
Successful 3D integration of a stacked chip fabricated by a "chip-level through-silicon-via (TSV)" process was confirmed by inter-chip data transmission. According to measurements of the electrical properties of the stacked chip, structural design of TSV contact wiring is very important fo...
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| creator | Hozawa, K. Furuta, F. Hanaoka, Y. Aoki, M. Osada, K. Takeda, K. Kang Wook Lee Fukushima, T. Koyanagi, M. |
| description | Successful 3D integration of a stacked chip fabricated by a "chip-level through-silicon-via (TSV)" process was confirmed by inter-chip data transmission. According to measurements of the electrical properties of the stacked chip, structural design of TSV contact wiring is very important for chip-level/via-last TSV integration. That is, the design influences TSV contact resistance, TSV coupling capacitance, and wiring capacitance of the surrounding Cu/low-k interconnections. |
| doi_str_mv | 10.1109/VLSIT.2012.6242518 |
| format | Conference Proceeding |
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According to measurements of the electrical properties of the stacked chip, structural design of TSV contact wiring is very important for chip-level/via-last TSV integration. That is, the design influences TSV contact resistance, TSV coupling capacitance, and wiring capacitance of the surrounding Cu/low-k interconnections.</description><identifier>ISSN: 0743-1562</identifier><identifier>ISBN: 9781467308465</identifier><identifier>ISBN: 1467308463</identifier><identifier>EISBN: 9781467308472</identifier><identifier>EISBN: 1467308471</identifier><identifier>DOI: 10.1109/VLSIT.2012.6242518</identifier><language>eng ; jpn</language><publisher>IEEE</publisher><subject>Capacitance ; Contacts ; Data communication ; Metals ; Semiconductor device measurement ; Through-silicon vias ; Wiring</subject><ispartof>2012 Symposium on VLSI Technology (VLSIT), 2012, p.175-176</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6242518$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6242518$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Hozawa, K.</creatorcontrib><creatorcontrib>Furuta, F.</creatorcontrib><creatorcontrib>Hanaoka, Y.</creatorcontrib><creatorcontrib>Aoki, M.</creatorcontrib><creatorcontrib>Osada, K.</creatorcontrib><creatorcontrib>Takeda, K.</creatorcontrib><creatorcontrib>Kang Wook Lee</creatorcontrib><creatorcontrib>Fukushima, T.</creatorcontrib><creatorcontrib>Koyanagi, M.</creatorcontrib><title>Demonstration of inter-chip data transmission in a three-dimensional stacked chip fabricated by chip-level TSV integration</title><title>2012 Symposium on VLSI Technology (VLSIT)</title><addtitle>VLSIT</addtitle><description>Successful 3D integration of a stacked chip fabricated by a "chip-level through-silicon-via (TSV)" process was confirmed by inter-chip data transmission. According to measurements of the electrical properties of the stacked chip, structural design of TSV contact wiring is very important for chip-level/via-last TSV integration. That is, the design influences TSV contact resistance, TSV coupling capacitance, and wiring capacitance of the surrounding Cu/low-k interconnections.</description><subject>Capacitance</subject><subject>Contacts</subject><subject>Data communication</subject><subject>Metals</subject><subject>Semiconductor device measurement</subject><subject>Through-silicon vias</subject><subject>Wiring</subject><issn>0743-1562</issn><isbn>9781467308465</isbn><isbn>1467308463</isbn><isbn>9781467308472</isbn><isbn>1467308471</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2012</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpVkM1OwzAQhI0AiVL6AnDxC7j4b-3kiAqFSpU4tPRa2c6GGpK0iiOk8vSkPxdOq_lGOztaQu4FHwvB88fVfDFbjiUXcmykliCyCzLKbSa0sYpn2srLf9rAFRlwqxUTYOQNuU3pi3PJQWUD8vuM9bZJXeu6uG3otqSx6bBlYRN3tHCdo73VpDqmdPBjQ3uyaRFZEWtsDtBVNHUufGNBj1ul820Mruu13x8Rq_AHK7pcrI7pn6djd-S6dFXC0XkOycf0ZTl5Y_P319nkac5i37djwYJTwKUvgIuQi9yEoEWpbQHorTAaCgADEEqecY3SeZeDz9F7hUpzVEPycMqNiLjetbF27X59fp36A31aYnQ</recordid><startdate>201206</startdate><enddate>201206</enddate><creator>Hozawa, K.</creator><creator>Furuta, F.</creator><creator>Hanaoka, Y.</creator><creator>Aoki, M.</creator><creator>Osada, K.</creator><creator>Takeda, K.</creator><creator>Kang Wook Lee</creator><creator>Fukushima, T.</creator><creator>Koyanagi, M.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>201206</creationdate><title>Demonstration of inter-chip data transmission in a three-dimensional stacked chip fabricated by chip-level TSV integration</title><author>Hozawa, K. ; Furuta, F. ; Hanaoka, Y. ; Aoki, M. ; Osada, K. ; Takeda, K. ; Kang Wook Lee ; Fukushima, T. ; Koyanagi, M.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i156t-c75a3502bd501c9196cc41f47d5eb71645d55655cf0804e2aba95b9ebb3e340e3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng ; jpn</language><creationdate>2012</creationdate><topic>Capacitance</topic><topic>Contacts</topic><topic>Data communication</topic><topic>Metals</topic><topic>Semiconductor device measurement</topic><topic>Through-silicon vias</topic><topic>Wiring</topic><toplevel>online_resources</toplevel><creatorcontrib>Hozawa, K.</creatorcontrib><creatorcontrib>Furuta, F.</creatorcontrib><creatorcontrib>Hanaoka, Y.</creatorcontrib><creatorcontrib>Aoki, M.</creatorcontrib><creatorcontrib>Osada, K.</creatorcontrib><creatorcontrib>Takeda, K.</creatorcontrib><creatorcontrib>Kang Wook Lee</creatorcontrib><creatorcontrib>Fukushima, T.</creatorcontrib><creatorcontrib>Koyanagi, M.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Hozawa, K.</au><au>Furuta, F.</au><au>Hanaoka, Y.</au><au>Aoki, M.</au><au>Osada, K.</au><au>Takeda, K.</au><au>Kang Wook Lee</au><au>Fukushima, T.</au><au>Koyanagi, M.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Demonstration of inter-chip data transmission in a three-dimensional stacked chip fabricated by chip-level TSV integration</atitle><btitle>2012 Symposium on VLSI Technology (VLSIT)</btitle><stitle>VLSIT</stitle><date>2012-06</date><risdate>2012</risdate><spage>175</spage><epage>176</epage><pages>175-176</pages><issn>0743-1562</issn><isbn>9781467308465</isbn><isbn>1467308463</isbn><eisbn>9781467308472</eisbn><eisbn>1467308471</eisbn><abstract>Successful 3D integration of a stacked chip fabricated by a "chip-level through-silicon-via (TSV)" process was confirmed by inter-chip data transmission. According to measurements of the electrical properties of the stacked chip, structural design of TSV contact wiring is very important for chip-level/via-last TSV integration. That is, the design influences TSV contact resistance, TSV coupling capacitance, and wiring capacitance of the surrounding Cu/low-k interconnections.</abstract><pub>IEEE</pub><doi>10.1109/VLSIT.2012.6242518</doi><tpages>2</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0743-1562 |
| ispartof | 2012 Symposium on VLSI Technology (VLSIT), 2012, p.175-176 |
| issn | 0743-1562 |
| language | eng ; jpn |
| recordid | cdi_ieee_primary_6242518 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Capacitance Contacts Data communication Metals Semiconductor device measurement Through-silicon vias Wiring |
| title | Demonstration of inter-chip data transmission in a three-dimensional stacked chip fabricated by chip-level TSV integration |
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