Demonstration of inter-chip data transmission in a three-dimensional stacked chip fabricated by chip-level TSV integration

Successful 3D integration of a stacked chip fabricated by a "chip-level through-silicon-via (TSV)" process was confirmed by inter-chip data transmission. According to measurements of the electrical properties of the stacked chip, structural design of TSV contact wiring is very important for chip-level/via-last TSV integration. That is, the design influences TSV contact resistance, TSV coupling capacitance, and wiring capacitance of the surrounding Cu/low-k interconnections.