Integration of 4F2 selector-less crossbar array 2Mb ReRAM based on transition metal oxides for high density memory applications

4F 2 selector-less crossbar array 2Mb ReRAM test chip with 54nm technology has been successfully integrated for high cell efficiency and high density memory applications by implementing parts of decoders to row/column lines directly under the cell area. Read/write specifications for memory operation...

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Hauptverfasser: Hyung Dong Lee, Kim, S. G., Cho, K., Hwang, H., Choi, H., Lee, J., Lee, S. H., Lee, H. J., Suh, J., Chung, S., Kim, Y. S., Kim, K. S., Nam, W. S., Cheong, J. T., Kim, J. T., Chae, S., Hwang, E., Park, S. N., Sohn, Y. S., Lee, C. G., Shin, H. S., Lee, K. J., Hong, K., Jeong, H. G., Rho, K. M., Kim, Y. K., Nickel, J., Yang, J. J., Cho, H. S., Perner, F., Williams, R. S., Lee, J. H., Park, S. K., Hong, S.
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Sprache:eng
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Zusammenfassung:4F 2 selector-less crossbar array 2Mb ReRAM test chip with 54nm technology has been successfully integrated for high cell efficiency and high density memory applications by implementing parts of decoders to row/column lines directly under the cell area. Read/write specifications for memory operation in a chip are presented by minimizing sneak current through unselected cells. The characteristics of memory cell (nonlinearity, Kw >;8, Iop
ISSN:0743-1562
DOI:10.1109/VLSIT.2012.6242506