Robust PEALD SiN spacer for gate first high-k metal gate integration

Robust PEALD SiN spacer for gate first high-k metal gate integration

As we packed more and more transistors into one chip and as the size of transistor continues to shrink, the need for conformal sidewall protection layer becomes critical. In this work improved device properties is demonstrated using PEALD SiN spacer compared to the conventional PECVD SiN spacer.

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Bibliographische Detailangaben
Hauptverfasser: Triyoso, D. H., Jaschke, V., Shu, J., Mutas, S., Hempel, K., Schaeffer, J. K., Lenski, M.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
ALD
Atomic layer deposition
high-k metal gate
iso-dense loading
Loading
Logic gates
Plasma temperature
Silicon compounds
SiN
spacer
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Beschreibung
Zusammenfassung:As we packed more and more transistors into one chip and as the size of transistor continues to shrink, the need for conformal sidewall protection layer becomes critical. In this work improved device properties is demonstrated using PEALD SiN spacer compared to the conventional PECVD SiN spacer.
ISSN:2381-3555
2691-0462
DOI:10.1109/ICICDT.2012.6232870