Ultra low-voltage and high speed dynamic and static CMOS precharge logic
In this paper we present novel high speed and ultra low voltage domino invererters. The delay of the inverters are less than 4% of the delay for a standard CMOS inverter. A low power inverter is included and the simulated data for supply voltages in the range of 200mV to 400mV are provoded. Monte ca...
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| creator | Berg, Y. Mirmotahari, O. |
| description | In this paper we present novel high speed and ultra low voltage domino invererters. The delay of the inverters are less than 4% of the delay for a standard CMOS inverter. A low power inverter is included and the simulated data for supply voltages in the range of 200mV to 400mV are provoded. Monte carlo simulation show that the ULV logic styles are less influenced by process mismatches than standard CMOS logic. Simulated data presented is obtained by HSpice and process parameters for the 90nm TSMC process. |
| doi_str_mv | 10.1109/FTFC.2012.6231718 |
| format | Conference Proceeding |
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The delay of the inverters are less than 4% of the delay for a standard CMOS inverter. A low power inverter is included and the simulated data for supply voltages in the range of 200mV to 400mV are provoded. Monte carlo simulation show that the ULV logic styles are less influenced by process mismatches than standard CMOS logic. Simulated data presented is obtained by HSpice and process parameters for the 90nm TSMC process.</description><subject>CMOS integrated circuits</subject><subject>Delay</subject><subject>Inverters</subject><subject>Logic gates</subject><subject>MOS devices</subject><subject>Transistors</subject><isbn>1467308226</isbn><isbn>9781467308229</isbn><isbn>9781467308212</isbn><isbn>146730820X</isbn><isbn>1467308218</isbn><isbn>9781467308205</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2012</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1T8tKw0AUHRFBrfkAcTM_kDiPZB5LCcYKlS6M63IzcycZSZuQBKV_b9F6NucB58Ah5J6zjHNmH6u6KjPBuMiUkFxzc0ESqw3PlZbMCC4uye2_EeqaJPP8yU7QBTOW35D1R79MQPvhO_0a-gVapHDwtIttR-cR0VN_PMA-ut94XmA5yfJt-07HCV0H06nQD210d-QqQD9jcuYVqavnulynm-3La_m0SaNlS-qxEcEphtKZAEwptIUpuM8xqMbm2mHROIvAc-uZAi5CY40GKaUIQqpcrsjD32xExN04xT1Mx935u_wB50NMpA</recordid><startdate>201206</startdate><enddate>201206</enddate><creator>Berg, Y.</creator><creator>Mirmotahari, O.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201206</creationdate><title>Ultra low-voltage and high speed dynamic and static CMOS precharge logic</title><author>Berg, Y. ; Mirmotahari, O.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-deb2fc60e3c8fa066e95851d4ef6b947ce5bc9ea149d06a12fb987a3332f23643</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2012</creationdate><topic>CMOS integrated circuits</topic><topic>Delay</topic><topic>Inverters</topic><topic>Logic gates</topic><topic>MOS devices</topic><topic>Transistors</topic><toplevel>online_resources</toplevel><creatorcontrib>Berg, Y.</creatorcontrib><creatorcontrib>Mirmotahari, O.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Berg, Y.</au><au>Mirmotahari, O.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Ultra low-voltage and high speed dynamic and static CMOS precharge logic</atitle><btitle>2012 IEEE Faible Tension Faible Consommation</btitle><stitle>FTFC</stitle><date>2012-06</date><risdate>2012</risdate><spage>1</spage><epage>4</epage><pages>1-4</pages><isbn>1467308226</isbn><isbn>9781467308229</isbn><eisbn>9781467308212</eisbn><eisbn>146730820X</eisbn><eisbn>1467308218</eisbn><eisbn>9781467308205</eisbn><abstract>In this paper we present novel high speed and ultra low voltage domino invererters. The delay of the inverters are less than 4% of the delay for a standard CMOS inverter. A low power inverter is included and the simulated data for supply voltages in the range of 200mV to 400mV are provoded. Monte carlo simulation show that the ULV logic styles are less influenced by process mismatches than standard CMOS logic. Simulated data presented is obtained by HSpice and process parameters for the 90nm TSMC process.</abstract><pub>IEEE</pub><doi>10.1109/FTFC.2012.6231718</doi><tpages>4</tpages></addata></record> |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | CMOS integrated circuits Delay Inverters Logic gates MOS devices Transistors |
| title | Ultra low-voltage and high speed dynamic and static CMOS precharge logic |
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