Ultra low-voltage and high speed dynamic and static CMOS precharge logic

In this paper we present novel high speed and ultra low voltage domino invererters. The delay of the inverters are less than 4% of the delay for a standard CMOS inverter. A low power inverter is included and the simulated data for supply voltages in the range of 200mV to 400mV are provoded. Monte carlo simulation show that the ULV logic styles are less influenced by process mismatches than standard CMOS logic. Simulated data presented is obtained by HSpice and process parameters for the 90nm TSMC process.