Analysis of a drain-voltage oscillation of MOSFET under high dV/dt UIS condition

Analysis of a drain-voltage oscillation of MOSFET under high dV/dt UIS condition

In this paper, we investigate a mechanism of drain-voltage oscillation of MOSFET under high dV/dt UIS condition by using numerical simulation and experiments. One of the trigger events of the oscillation is found to be the current path switching between the active region and the termination region w...

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Hauptverfasser: Soneda, Shinya, Narazaki, A., Takahashi, T., Takano, K., Kido, S., Fukada, Y., Taguchi, K., Terashima, T.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Avalanche
MOSFET
Numerical simulation
Oscillation
Oscillators
Power MOSFET
Simulation
Switches
Temperature distribution
UIS
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Beschreibung
Zusammenfassung:In this paper, we investigate a mechanism of drain-voltage oscillation of MOSFET under high dV/dt UIS condition by using numerical simulation and experiments. One of the trigger events of the oscillation is found to be the current path switching between the active region and the termination region with close BVDSS characteristics. By optimizing the device parameters to make appropriate the BVDSS balance, avalanche capability is improved over ~ 40%, enabling the oscillation-free turn-off.
ISSN:1063-6854
1946-0201
DOI:10.1109/ISPSD.2012.6229046