A 90 to 170V scalable P-LDMOS with accompanied high voltage PJFET

A 90 to 170V scalable P-LDMOS with accompanied high voltage PJFET

A novel JFET redesign of a laterally scaled P-LDMOS device is presented. The P-LDMOS device has excellent Rsp as it is scaled from 90V to 170V operation. This P-LDMOS design is modified to produce a 100V PJFET with good turn-off characteristics and a relatively low Vpinch of 3-7V.

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Bibliographische Detailangaben
Hauptverfasser: Ellis-Monaghan, J., Yun Shi, Sharma, S., Feilchenfeld, N., Letavic, T., Phelps, R., Hedges, C., Cook, D., Dunn, J.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Breakdown voltage
Electric breakdown
Electric potential
Impact ionization
JFETs
Junctions
LDMOS
Logic gates
PJFET
PLDMOS
Power MOSFET
RESURF
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Beschreibung
Zusammenfassung:A novel JFET redesign of a laterally scaled P-LDMOS device is presented. The P-LDMOS device has excellent Rsp as it is scaled from 90V to 170V operation. This P-LDMOS design is modified to produce a 100V PJFET with good turn-off characteristics and a relatively low Vpinch of 3-7V.
ISSN:1063-6854
1946-0201
DOI:10.1109/ISPSD.2012.6229040