Improvements in low temperature (<625°C) FDSOI devices down to 30nm gate length

Improvements in low temperature (<625°C) FDSOI devices down to 30nm gate length

For the first time, low temperature (LT) anneal at 625°C has been demonstrated for dopants activation enabling similar ION/IOFF trade-off as standard spike anneal (>;1000°C), down to 30nm gate length (LG) for both n&p FETs. Similar short channel effect control has been achieved in LT n&p...

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Hauptverfasser: Xu, C., Batude, P., Vinet, M., Mouis, M., Casse, M., Sklenard, B., Colombeau, B., Rafhay, Q., Tabone, C., Berthoz, J., Previtali, B., Mazurier, J., Brunet, L., Brevard, L., Khaja, F. A., Hartmann, J., Allain, F., Toffoli, A., Kies, R., Le Royer, C., Morvan, S., Pouydebasque, A., Garros, X., Pakfar, A., Tavernier, C., Faynot, O., Poiroux, T.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Annealing
Engineering Sciences
FETs
Implants
Logic gates
Micro and nanotechnologies
Microelectronics
Performance evaluation
Silicon
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Beschreibung
Zusammenfassung:For the first time, low temperature (LT) anneal at 625°C has been demonstrated for dopants activation enabling similar ION/IOFF trade-off as standard spike anneal (>;1000°C), down to 30nm gate length (LG) for both n&p FETs. Similar short channel effect control has been achieved in LT n&p FETs as its high temperature (HT) counterparts. Influence of dopant implant tilt on LT device performance is analyzed and guidelines for device performance optimization are proposed. This demonstration paves the way to 3D sequential integration with equal performance for stacked transistors and for bottom transistors.
ISSN:1524-766X
2690-8174
DOI:10.1109/VLSI-TSA.2012.6210171