A high performance reconfigurable RSA processor

A reconfigurable cryptographic processor which can perform either prime field GF(p) operation or binary extension field GF(2 m ) operation for arbitrary prime numbers, irreducible polynomials and precisions with a reconfigurable data path in their microcode based architecture. Users are capable of programming cryptographic algorithm in microcode sequence with a majority of public key cryptographic algorithms such as Rivest-Shamir-Adleman (RSA) and Elliptic Curve Cryptography (ECC). Also the developed processor should have full cryptography algorithm flexibility, high hardware utilization and high performance. The architecture would be modeled using Verilog and synthesized using Synopsis Synthesis tool.