A 100MHz S/s, 7 bit VCO-based ADC which is used in time interleaved ADC architectures
In this paper, principles of time interleaved ADC and VCO-based ADC architectures are introduced. A design of VCO-based ADC which is suitable to be used in time interleaved ADC architectures is presented. In the design, a high speed sample and hold circuit is realized for wideband input, multi phase...
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 7 |
|---|---|
| container_issue | |
| container_start_page | 4 |
| container_title | |
| container_volume | |
| creator | Ruihao Si Fule Li Chun Zhang |
| description | In this paper, principles of time interleaved ADC and VCO-based ADC architectures are introduced. A design of VCO-based ADC which is suitable to be used in time interleaved ADC architectures is presented. In the design, a high speed sample and hold circuit is realized for wideband input, multi phase ring oscillator is adopted in order to increase time resolution, multi phase edge counter is used to complete the quantization process. The proposed ADC is designed in UMC 0.18μm technology. Simulation results show the proposed architecture can reach 7 bit output resolution at 100MHz speed of sample per second when a 1.037GHz input signal is applied. The proposed VCO-based ADC architecture is technology friendly for low power consumption compared to OPAMP-based ADC architectures at similar speed. This merit enables VCO-based ADC compatible to be used in time interleaved ADC architectures as technology proceeds. |
| doi_str_mv | 10.1109/CECNet.2012.6202063 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_6202063</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6202063</ieee_id><sourcerecordid>6202063</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-b2669a3c24de847fe57599988f8cb5d04550b6d505d4f02c5e0d7038009cafb53</originalsourceid><addsrcrecordid>eNpVkM9KAzEYxCMiKHWfoJc8gNt-yebvcVmrFao9WL2WbPItG2lFNqmiT9-Ke3EuP2YY5jCETBnMGAM7bxbNE-YZB8ZnigMHVZ2RwmrDhNSaCVbZ839eqEtSpPQGJ2ngRtgr8lJTBvC4_KHP83RDNW1jpq_NumxdwkDr24Z-9dH3NCZ6-E3iO81xjydmHHboPseWG3wfM_p8GDBdk4vO7RIWIydkc7fYNMtytb5_aOpVGS3ksuVKWVd5LgIaoTuUWlprjemMb2UAISW0KkiQQXTAvUQIGioDYL3rWllNyPRvNiLi9mOIezd8b8cvqiOP1k9H</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A 100MHz S/s, 7 bit VCO-based ADC which is used in time interleaved ADC architectures</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Ruihao Si ; Fule Li ; Chun Zhang</creator><creatorcontrib>Ruihao Si ; Fule Li ; Chun Zhang</creatorcontrib><description>In this paper, principles of time interleaved ADC and VCO-based ADC architectures are introduced. A design of VCO-based ADC which is suitable to be used in time interleaved ADC architectures is presented. In the design, a high speed sample and hold circuit is realized for wideband input, multi phase ring oscillator is adopted in order to increase time resolution, multi phase edge counter is used to complete the quantization process. The proposed ADC is designed in UMC 0.18μm technology. Simulation results show the proposed architecture can reach 7 bit output resolution at 100MHz speed of sample per second when a 1.037GHz input signal is applied. The proposed VCO-based ADC architecture is technology friendly for low power consumption compared to OPAMP-based ADC architectures at similar speed. This merit enables VCO-based ADC compatible to be used in time interleaved ADC architectures as technology proceeds.</description><identifier>ISBN: 9781457714146</identifier><identifier>ISBN: 1457714140</identifier><identifier>EISBN: 9781457714139</identifier><identifier>EISBN: 9781457714153</identifier><identifier>EISBN: 1457714132</identifier><identifier>EISBN: 1457714159</identifier><identifier>DOI: 10.1109/CECNet.2012.6202063</identifier><language>eng</language><publisher>IEEE</publisher><subject>Capacitance ; Clocks ; Computer architecture ; Delay ; Multi phase ring oscillator ; Quantization ; Ring oscillators ; Sample and hold clock ; Time interleaved ADC ; Transistors ; VCO-based ADC ; Voltage-controlled oscillators</subject><ispartof>2012 2nd International Conference on Consumer Electronics, Communications and Networks (CECNet), 2012, p.4-7</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6202063$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6202063$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Ruihao Si</creatorcontrib><creatorcontrib>Fule Li</creatorcontrib><creatorcontrib>Chun Zhang</creatorcontrib><title>A 100MHz S/s, 7 bit VCO-based ADC which is used in time interleaved ADC architectures</title><title>2012 2nd International Conference on Consumer Electronics, Communications and Networks (CECNet)</title><addtitle>CECNet</addtitle><description>In this paper, principles of time interleaved ADC and VCO-based ADC architectures are introduced. A design of VCO-based ADC which is suitable to be used in time interleaved ADC architectures is presented. In the design, a high speed sample and hold circuit is realized for wideband input, multi phase ring oscillator is adopted in order to increase time resolution, multi phase edge counter is used to complete the quantization process. The proposed ADC is designed in UMC 0.18μm technology. Simulation results show the proposed architecture can reach 7 bit output resolution at 100MHz speed of sample per second when a 1.037GHz input signal is applied. The proposed VCO-based ADC architecture is technology friendly for low power consumption compared to OPAMP-based ADC architectures at similar speed. This merit enables VCO-based ADC compatible to be used in time interleaved ADC architectures as technology proceeds.</description><subject>Capacitance</subject><subject>Clocks</subject><subject>Computer architecture</subject><subject>Delay</subject><subject>Multi phase ring oscillator</subject><subject>Quantization</subject><subject>Ring oscillators</subject><subject>Sample and hold clock</subject><subject>Time interleaved ADC</subject><subject>Transistors</subject><subject>VCO-based ADC</subject><subject>Voltage-controlled oscillators</subject><isbn>9781457714146</isbn><isbn>1457714140</isbn><isbn>9781457714139</isbn><isbn>9781457714153</isbn><isbn>1457714132</isbn><isbn>1457714159</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2012</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpVkM9KAzEYxCMiKHWfoJc8gNt-yebvcVmrFao9WL2WbPItG2lFNqmiT9-Ke3EuP2YY5jCETBnMGAM7bxbNE-YZB8ZnigMHVZ2RwmrDhNSaCVbZ839eqEtSpPQGJ2ngRtgr8lJTBvC4_KHP83RDNW1jpq_NumxdwkDr24Z-9dH3NCZ6-E3iO81xjydmHHboPseWG3wfM_p8GDBdk4vO7RIWIydkc7fYNMtytb5_aOpVGS3ksuVKWVd5LgIaoTuUWlprjemMb2UAISW0KkiQQXTAvUQIGioDYL3rWllNyPRvNiLi9mOIezd8b8cvqiOP1k9H</recordid><startdate>201204</startdate><enddate>201204</enddate><creator>Ruihao Si</creator><creator>Fule Li</creator><creator>Chun Zhang</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201204</creationdate><title>A 100MHz S/s, 7 bit VCO-based ADC which is used in time interleaved ADC architectures</title><author>Ruihao Si ; Fule Li ; Chun Zhang</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-b2669a3c24de847fe57599988f8cb5d04550b6d505d4f02c5e0d7038009cafb53</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2012</creationdate><topic>Capacitance</topic><topic>Clocks</topic><topic>Computer architecture</topic><topic>Delay</topic><topic>Multi phase ring oscillator</topic><topic>Quantization</topic><topic>Ring oscillators</topic><topic>Sample and hold clock</topic><topic>Time interleaved ADC</topic><topic>Transistors</topic><topic>VCO-based ADC</topic><topic>Voltage-controlled oscillators</topic><toplevel>online_resources</toplevel><creatorcontrib>Ruihao Si</creatorcontrib><creatorcontrib>Fule Li</creatorcontrib><creatorcontrib>Chun Zhang</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Ruihao Si</au><au>Fule Li</au><au>Chun Zhang</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A 100MHz S/s, 7 bit VCO-based ADC which is used in time interleaved ADC architectures</atitle><btitle>2012 2nd International Conference on Consumer Electronics, Communications and Networks (CECNet)</btitle><stitle>CECNet</stitle><date>2012-04</date><risdate>2012</risdate><spage>4</spage><epage>7</epage><pages>4-7</pages><isbn>9781457714146</isbn><isbn>1457714140</isbn><eisbn>9781457714139</eisbn><eisbn>9781457714153</eisbn><eisbn>1457714132</eisbn><eisbn>1457714159</eisbn><abstract>In this paper, principles of time interleaved ADC and VCO-based ADC architectures are introduced. A design of VCO-based ADC which is suitable to be used in time interleaved ADC architectures is presented. In the design, a high speed sample and hold circuit is realized for wideband input, multi phase ring oscillator is adopted in order to increase time resolution, multi phase edge counter is used to complete the quantization process. The proposed ADC is designed in UMC 0.18μm technology. Simulation results show the proposed architecture can reach 7 bit output resolution at 100MHz speed of sample per second when a 1.037GHz input signal is applied. The proposed VCO-based ADC architecture is technology friendly for low power consumption compared to OPAMP-based ADC architectures at similar speed. This merit enables VCO-based ADC compatible to be used in time interleaved ADC architectures as technology proceeds.</abstract><pub>IEEE</pub><doi>10.1109/CECNet.2012.6202063</doi><tpages>4</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISBN: 9781457714146 |
| ispartof | 2012 2nd International Conference on Consumer Electronics, Communications and Networks (CECNet), 2012, p.4-7 |
| issn | |
| language | eng |
| recordid | cdi_ieee_primary_6202063 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Capacitance Clocks Computer architecture Delay Multi phase ring oscillator Quantization Ring oscillators Sample and hold clock Time interleaved ADC Transistors VCO-based ADC Voltage-controlled oscillators |
| title | A 100MHz S/s, 7 bit VCO-based ADC which is used in time interleaved ADC architectures |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-27T14%3A18%3A37IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20100MHz%20S/s,%207%20bit%20VCO-based%20ADC%20which%20is%20used%20in%20time%20interleaved%20ADC%20architectures&rft.btitle=2012%202nd%20International%20Conference%20on%20Consumer%20Electronics,%20Communications%20and%20Networks%20(CECNet)&rft.au=Ruihao%20Si&rft.date=2012-04&rft.spage=4&rft.epage=7&rft.pages=4-7&rft.isbn=9781457714146&rft.isbn_list=1457714140&rft_id=info:doi/10.1109/CECNet.2012.6202063&rft_dat=%3Cieee_6IE%3E6202063%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781457714139&rft.eisbn_list=9781457714153&rft.eisbn_list=1457714132&rft.eisbn_list=1457714159&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6202063&rfr_iscdi=true |