Decision Feedback Equalizer Architectures With Multiple Continuous-Time Infinite Impulse Response Filters

Decision feedback equalizer (DFE) architectures with varying numbers of discrete-time taps and continuous-time infinite impulse response (IIR) filters are compared for use in typical wireline channels. In each case, the DFE coefficients are optimized to minimize a cost function that equally weights both jitter and vertical eye opening. Even when some reflections are present (e.g., backplane channels) continuous-time IIR taps can be effective if their filter coefficients are properly optimized. Using a DFE architecture with only two IIR filters provides adequate results for both a 26-dB loss coax cable and a 16" FR-4 backplane channel at 10 Gb/s while keeping the DFE complexity low. Furthermore, the implementation and experimental results of a DFE with multiple (three) IIR filters is reported. Fabricated in a 0.13 μm CMOS process, the DFE consumes 17.3 mW from a 1.2 V supply. A bit error rate (BER) of 10 -12 was achieved at a data rate of 3.7 Gb/s.