High speed circuit techniques in a 150 MHz 64 M SDRAM

High speed circuit techniques in a 150 MHz 64 M SDRAM

This paper outlines three methods used to decrease the access time in a 64 M SDRAM. The access time from the read command, Taa, is reduced by the use of a novel column redundancy scheme with easy programming and by the use of current sensing in the data output path. The access time from the clock, T...

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Bibliographische Detailangaben
Hauptverfasser: Lines, V., Abou-Seido, M., Mar, C., Achyuthan, A., Miyamoto, S., Murashima, Y., Sakuma, S.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuit faults
Clocks
Decoding
Delay
Fuses
Integrated circuit interconnections
Redundancy
SDRAM
Technological innovation
Testing
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Beschreibung
Zusammenfassung:This paper outlines three methods used to decrease the access time in a 64 M SDRAM. The access time from the read command, Taa, is reduced by the use of a novel column redundancy scheme with easy programming and by the use of current sensing in the data output path. The access time from the clock, Tac, is reduced by the use of a digital DLL whose functionality can be tested with on chip test functions.
ISSN:1087-4852
2576-9154
DOI:10.1109/MTDT.1997.619388