Analysis of gate capacitance of n-type junctionless transistors using three-dimensional device simulations
Junctionless transistors can be an excellent alternative for extremely scaled MOSFETs as they present a good behavior with no doping gradients between channel and source/drain regions. This paper aims at analyzing the gate capacitance (C gg ) of junctionless transistors dependence with the three mos...
Gespeichert in:
Hauptverfasser: | , , , , |
---|---|
Format: | Tagungsbericht |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | 4 |
---|---|
container_issue | |
container_start_page | 1 |
container_title | |
container_volume | |
creator | Mariniello, G. Doria, R. T. de Souza, M. Pavanello, M. A. Trevisoli, R. D. |
description | Junctionless transistors can be an excellent alternative for extremely scaled MOSFETs as they present a good behavior with no doping gradients between channel and source/drain regions. This paper aims at analyzing the gate capacitance (C gg ) of junctionless transistors dependence with the three most important technological parameters for these devices: doping concentration (N D ), fin width (W fin ) and fin height (H fin ). |
doi_str_mv | 10.1109/ICCDCS.2012.6188946 |
format | Conference Proceeding |
fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_6188946</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6188946</ieee_id><sourcerecordid>6188946</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-815e457e6b5dca444a8034380f048949082e4f3aaf420533239064865de7b8d53</originalsourceid><addsrcrecordid>eNo1kMtuwjAQRV21lUopX8DGPxA6fsZeovSFhNRF2SOTTKhRcFDsVOLva1Q6m6uZ0T26M4TMGSwYA_u8qqqX6mvBgfGFZsZYqW_II5OqLBljpb4lM1ua_17bOzLhTKtCKMkfyCzGA-QqQYC2E3JYBtedo4-0b-neJaS1O7naJxdqvMxCkc4npIcx1Mn3ocMYaRpcyJbUD5GO0Yc9Td8DYtH4I-ZFn5G0wR-fCdEfx85dnPGJ3Leuizi76pRs3l431Uex_nxfVct14S2kwjCFOTvqnWpqJ6V0BoQUBlqQ-VYLhqNshXOt5KCE4MKClkarBsudaZSYkvkf1iPi9jT4oxvO2-unxC-u6Fww</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Analysis of gate capacitance of n-type junctionless transistors using three-dimensional device simulations</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Mariniello, G. ; Doria, R. T. ; de Souza, M. ; Pavanello, M. A. ; Trevisoli, R. D.</creator><creatorcontrib>Mariniello, G. ; Doria, R. T. ; de Souza, M. ; Pavanello, M. A. ; Trevisoli, R. D.</creatorcontrib><description>Junctionless transistors can be an excellent alternative for extremely scaled MOSFETs as they present a good behavior with no doping gradients between channel and source/drain regions. This paper aims at analyzing the gate capacitance (C gg ) of junctionless transistors dependence with the three most important technological parameters for these devices: doping concentration (N D ), fin width (W fin ) and fin height (H fin ).</description><identifier>ISSN: 2165-3542</identifier><identifier>ISBN: 9781457711169</identifier><identifier>ISBN: 1457711168</identifier><identifier>EISBN: 1457711176</identifier><identifier>EISBN: 9781457711152</identifier><identifier>EISBN: 9781457711176</identifier><identifier>EISBN: 145771115X</identifier><identifier>DOI: 10.1109/ICCDCS.2012.6188946</identifier><language>eng</language><publisher>IEEE</publisher><subject>Conferences ; Gate Capacitance ; Junctionless Devices</subject><ispartof>2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS), 2012, p.1-4</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6188946$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6188946$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Mariniello, G.</creatorcontrib><creatorcontrib>Doria, R. T.</creatorcontrib><creatorcontrib>de Souza, M.</creatorcontrib><creatorcontrib>Pavanello, M. A.</creatorcontrib><creatorcontrib>Trevisoli, R. D.</creatorcontrib><title>Analysis of gate capacitance of n-type junctionless transistors using three-dimensional device simulations</title><title>2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)</title><addtitle>ICCDCS</addtitle><description>Junctionless transistors can be an excellent alternative for extremely scaled MOSFETs as they present a good behavior with no doping gradients between channel and source/drain regions. This paper aims at analyzing the gate capacitance (C gg ) of junctionless transistors dependence with the three most important technological parameters for these devices: doping concentration (N D ), fin width (W fin ) and fin height (H fin ).</description><subject>Conferences</subject><subject>Gate Capacitance</subject><subject>Junctionless Devices</subject><issn>2165-3542</issn><isbn>9781457711169</isbn><isbn>1457711168</isbn><isbn>1457711176</isbn><isbn>9781457711152</isbn><isbn>9781457711176</isbn><isbn>145771115X</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2012</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1kMtuwjAQRV21lUopX8DGPxA6fsZeovSFhNRF2SOTTKhRcFDsVOLva1Q6m6uZ0T26M4TMGSwYA_u8qqqX6mvBgfGFZsZYqW_II5OqLBljpb4lM1ua_17bOzLhTKtCKMkfyCzGA-QqQYC2E3JYBtedo4-0b-neJaS1O7naJxdqvMxCkc4npIcx1Mn3ocMYaRpcyJbUD5GO0Yc9Td8DYtH4I-ZFn5G0wR-fCdEfx85dnPGJ3Leuizi76pRs3l431Uex_nxfVct14S2kwjCFOTvqnWpqJ6V0BoQUBlqQ-VYLhqNshXOt5KCE4MKClkarBsudaZSYkvkf1iPi9jT4oxvO2-unxC-u6Fww</recordid><startdate>201203</startdate><enddate>201203</enddate><creator>Mariniello, G.</creator><creator>Doria, R. T.</creator><creator>de Souza, M.</creator><creator>Pavanello, M. A.</creator><creator>Trevisoli, R. D.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201203</creationdate><title>Analysis of gate capacitance of n-type junctionless transistors using three-dimensional device simulations</title><author>Mariniello, G. ; Doria, R. T. ; de Souza, M. ; Pavanello, M. A. ; Trevisoli, R. D.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-815e457e6b5dca444a8034380f048949082e4f3aaf420533239064865de7b8d53</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2012</creationdate><topic>Conferences</topic><topic>Gate Capacitance</topic><topic>Junctionless Devices</topic><toplevel>online_resources</toplevel><creatorcontrib>Mariniello, G.</creatorcontrib><creatorcontrib>Doria, R. T.</creatorcontrib><creatorcontrib>de Souza, M.</creatorcontrib><creatorcontrib>Pavanello, M. A.</creatorcontrib><creatorcontrib>Trevisoli, R. D.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Mariniello, G.</au><au>Doria, R. T.</au><au>de Souza, M.</au><au>Pavanello, M. A.</au><au>Trevisoli, R. D.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Analysis of gate capacitance of n-type junctionless transistors using three-dimensional device simulations</atitle><btitle>2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)</btitle><stitle>ICCDCS</stitle><date>2012-03</date><risdate>2012</risdate><spage>1</spage><epage>4</epage><pages>1-4</pages><issn>2165-3542</issn><isbn>9781457711169</isbn><isbn>1457711168</isbn><eisbn>1457711176</eisbn><eisbn>9781457711152</eisbn><eisbn>9781457711176</eisbn><eisbn>145771115X</eisbn><abstract>Junctionless transistors can be an excellent alternative for extremely scaled MOSFETs as they present a good behavior with no doping gradients between channel and source/drain regions. This paper aims at analyzing the gate capacitance (C gg ) of junctionless transistors dependence with the three most important technological parameters for these devices: doping concentration (N D ), fin width (W fin ) and fin height (H fin ).</abstract><pub>IEEE</pub><doi>10.1109/ICCDCS.2012.6188946</doi><tpages>4</tpages></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | ISSN: 2165-3542 |
ispartof | 2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS), 2012, p.1-4 |
issn | 2165-3542 |
language | eng |
recordid | cdi_ieee_primary_6188946 |
source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Conferences Gate Capacitance Junctionless Devices |
title | Analysis of gate capacitance of n-type junctionless transistors using three-dimensional device simulations |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-31T19%3A52%3A42IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Analysis%20of%20gate%20capacitance%20of%20n-type%20junctionless%20transistors%20using%20three-dimensional%20device%20simulations&rft.btitle=2012%208th%20International%20Caribbean%20Conference%20on%20Devices,%20Circuits%20and%20Systems%20(ICCDCS)&rft.au=Mariniello,%20G.&rft.date=2012-03&rft.spage=1&rft.epage=4&rft.pages=1-4&rft.issn=2165-3542&rft.isbn=9781457711169&rft.isbn_list=1457711168&rft_id=info:doi/10.1109/ICCDCS.2012.6188946&rft_dat=%3Cieee_6IE%3E6188946%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=1457711176&rft.eisbn_list=9781457711152&rft.eisbn_list=9781457711176&rft.eisbn_list=145771115X&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6188946&rfr_iscdi=true |