Analysis of gate capacitance of n-type junctionless transistors using three-dimensional device simulations

Junctionless transistors can be an excellent alternative for extremely scaled MOSFETs as they present a good behavior with no doping gradients between channel and source/drain regions. This paper aims at analyzing the gate capacitance (C gg ) of junctionless transistors dependence with the three most important technological parameters for these devices: doping concentration (N D ), fin width (W fin ) and fin height (H fin ).