Drain current model for junctionless nanowire transistors

Drain current model for junctionless nanowire transistors

Junctionless Nanowire Transistors (JNT) are considered as promising devices for sub-20 nm era due to the great scalability they provide. This work proposes a physically based analytical model for the drain current in JNTs. The proposed model is continuous from the subthreshold region to the saturati...

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Bibliographische Detailangaben
Hauptverfasser: Trevisoli, R. D., Doria, R. T., de Souza, M., Pavanello, M. A.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Data models
Drain Current Model
Electric potential
Junctionless Devices
Logic gates
Neodymium
Silicon
Solid modeling
Transistors
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Beschreibung
Zusammenfassung:Junctionless Nanowire Transistors (JNT) are considered as promising devices for sub-20 nm era due to the great scalability they provide. This work proposes a physically based analytical model for the drain current in JNTs. The proposed model is continuous from the subthreshold region to the saturation. The model is validated with 3D TCAD simulation and experimental results.
ISSN:2165-3542
DOI:10.1109/ICCDCS.2012.6188924