Researches of Test Nodes Selection of Analog Circuit
Test nodes selection of analog circuit has great significance on fast, accurate circuit diagnosis, reduce test cost. For the lack of the current test nodes selection method of analog circuit, a test nodes selection method of analog circuit based on chaos immune clone selection optimization algorithm...
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| creator | Xu Qing-yao Cui Shao-hui Han Lu-jie Deng Shi-jie |
| description | Test nodes selection of analog circuit has great significance on fast, accurate circuit diagnosis, reduce test cost. For the lack of the current test nodes selection method of analog circuit, a test nodes selection method of analog circuit based on chaos immune clone selection optimization algorithm is presented in this paper. This method improves the efficiency and accuracy of test node selection. Finally the validity of this method is presented through circuit simulation. |
| doi_str_mv | 10.1109/ICCSEE.2012.367 |
| format | Conference Proceeding |
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Finally the validity of this method is presented through circuit simulation.</description><subject>analog circuit</subject><subject>Analog circuits</subject><subject>Chaos</subject><subject>chaos immune clone selection algorithm</subject><subject>Circuit faults</subject><subject>Cloning</subject><subject>Genetic algorithms</subject><subject>Heuristic algorithms</subject><subject>Optimization</subject><subject>test nodes optimal selection</subject><isbn>9781467306898</isbn><isbn>1467306894</isbn><isbn>9780769546476</isbn><isbn>0769546471</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2012</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotjMtOwzAQAI0QEqjkzIFLfiDF68d6fayiAJUqkGjulZ1swFJoUBwO_D3lcRrNHEaIG5BrAOnvtnW9b5q1kqDWGt2ZKLwj6dBbg8bh-a-DQaclkqdLUeScolTo0HoHV8K8cOYwd2-cy2koW85L-TT1J9vzyN2SpuNP3xzDOL2WdZq7z7Rci4shjJmLf65Ee9-09WO1e37Y1ptdlbxcqgDK9yZaMJZ6a10kq8AGFaVF9kikOqkHkr02KqrYGeZTIQleB-zZ65W4_dsmZj58zOk9zF8HBCJQTn8DcGBE6g</recordid><startdate>201203</startdate><enddate>201203</enddate><creator>Xu Qing-yao</creator><creator>Cui Shao-hui</creator><creator>Han Lu-jie</creator><creator>Deng Shi-jie</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201203</creationdate><title>Researches of Test Nodes Selection of Analog Circuit</title><author>Xu Qing-yao ; Cui Shao-hui ; Han Lu-jie ; Deng Shi-jie</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-a129d4b51458d557b85215a2b056e96882c03f80d342b2bc4ee2c080193a6de93</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2012</creationdate><topic>analog circuit</topic><topic>Analog circuits</topic><topic>Chaos</topic><topic>chaos immune clone selection algorithm</topic><topic>Circuit faults</topic><topic>Cloning</topic><topic>Genetic algorithms</topic><topic>Heuristic algorithms</topic><topic>Optimization</topic><topic>test nodes optimal selection</topic><toplevel>online_resources</toplevel><creatorcontrib>Xu Qing-yao</creatorcontrib><creatorcontrib>Cui Shao-hui</creatorcontrib><creatorcontrib>Han Lu-jie</creatorcontrib><creatorcontrib>Deng Shi-jie</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Xu Qing-yao</au><au>Cui Shao-hui</au><au>Han Lu-jie</au><au>Deng Shi-jie</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Researches of Test Nodes Selection of Analog Circuit</atitle><btitle>2012 International Conference on Computer Science and Electronics Engineering</btitle><stitle>iccsee</stitle><date>2012-03</date><risdate>2012</risdate><volume>3</volume><spage>16</spage><epage>19</epage><pages>16-19</pages><isbn>9781467306898</isbn><isbn>1467306894</isbn><eisbn>9780769546476</eisbn><eisbn>0769546471</eisbn><abstract>Test nodes selection of analog circuit has great significance on fast, accurate circuit diagnosis, reduce test cost. For the lack of the current test nodes selection method of analog circuit, a test nodes selection method of analog circuit based on chaos immune clone selection optimization algorithm is presented in this paper. This method improves the efficiency and accuracy of test node selection. Finally the validity of this method is presented through circuit simulation.</abstract><pub>IEEE</pub><doi>10.1109/ICCSEE.2012.367</doi><tpages>4</tpages></addata></record> |
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| ispartof | 2012 International Conference on Computer Science and Electronics Engineering, 2012, Vol.3, p.16-19 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | analog circuit Analog circuits Chaos chaos immune clone selection algorithm Circuit faults Cloning Genetic algorithms Heuristic algorithms Optimization test nodes optimal selection |
| title | Researches of Test Nodes Selection of Analog Circuit |
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