A dual 23Gb/s CMOS transmitter/receiver chipset for 40Gb/s RZ-DQPSK and CS-RZ-DQPSK optical transmission
This paper presents the first CMOS dual bitrate chipset with equalization in transmitter and receiver as well as a clock to data skew adjustment. Both the transmitter and the receiver consume less power than those in previously published results in the works of Hosida et al. (2007).
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| creator | Delong Cui Raghavan, B. Singh, U. Vasani, A. Zhi Huang Deyi Pi Khanpour, M. Nazemi, A. Maarefi, H. Ali, T. Huang, N. Wei Zhang Bo Zhang Momtaz, A. Jun Cao |
| description | This paper presents the first CMOS dual bitrate chipset with equalization in transmitter and receiver as well as a clock to data skew adjustment. Both the transmitter and the receiver consume less power than those in previously published results in the works of Hosida et al. (2007). |
| doi_str_mv | 10.1109/ISSCC.2012.6177006 |
| format | Conference Proceeding |
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| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0193-6530 |
| ispartof | 2012 IEEE International Solid-State Circuits Conference, 2012, p.330-332 |
| issn | 0193-6530 2376-8606 |
| language | eng |
| recordid | cdi_ieee_primary_6177006 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Clocks CMOS integrated circuits Jitter Optical filters Optical transmitters Receivers Solid state circuits |
| title | A dual 23Gb/s CMOS transmitter/receiver chipset for 40Gb/s RZ-DQPSK and CS-RZ-DQPSK optical transmission |
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