A dual 23Gb/s CMOS transmitter/receiver chipset for 40Gb/s RZ-DQPSK and CS-RZ-DQPSK optical transmission

A dual 23Gb/s CMOS transmitter/receiver chipset for 40Gb/s RZ-DQPSK and CS-RZ-DQPSK optical transmission

This paper presents the first CMOS dual bitrate chipset with equalization in transmitter and receiver as well as a clock to data skew adjustment. Both the transmitter and the receiver consume less power than those in previously published results in the works of Hosida et al. (2007).

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Bibliographische Detailangaben
Hauptverfasser: Delong Cui, Raghavan, B., Singh, U., Vasani, A., Zhi Huang, Deyi Pi, Khanpour, M., Nazemi, A., Maarefi, H., Ali, T., Huang, N., Wei Zhang, Bo Zhang, Momtaz, A., Jun Cao
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Clocks
CMOS integrated circuits
Jitter
Optical filters
Optical transmitters
Receivers
Solid state circuits
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Beschreibung
Zusammenfassung:This paper presents the first CMOS dual bitrate chipset with equalization in transmitter and receiver as well as a clock to data skew adjustment. Both the transmitter and the receiver consume less power than those in previously published results in the works of Hosida et al. (2007).
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2012.6177006