An LC bandpass ΔΣ ADC with 70dB SNDR over 20MHz bandwidth using CMOS DACs

Digitization from IF or RF using an LC bandpass ΔΣ modulator avoids the traditional problems of direct-conversion receivers, such as EVM degradation due to IQ imbalance, 2 nd -order intermodulation, and AGC interaction with DC offset correction settling. Our target application is a low-power IEEE 802.11n receiver for 2.4 to 2.5GHz using a fixed 3.2GHz clock and IF tuned from 700 to 800MHz. The fixed clock allows an integer-N PLL with high reference frequency (40MHz, for example), which allows wide loop bandwidth and low phase noise, even at mW-level power consumption (e.g. [1]). The power savings from simplified LO generation are also important. Sampling from IF with an f s /4 modulator rather than sampling from RF with a 3f s /4 modulator (as in [2]) gives higher ADC SNR because Q-enhanced LC filters have a tradeoff between Q and SNR and the loop filter fractional bandwidth is greater at the lower center frequency.