Layout-aware optimization of stt mrams

We present a layout-aware optimization methodology for spin-transfer torque (STT) MRAMs, considering the dependence of cell area on the access transistor width (W FET ), number of fingers in the access transistor and the metal pitch of bit- and source-lines. It is shown that for W FET less than a critical value (~7 times the minimum feature length), one-finger transistor yields minimum cell area. For large W FET , minimum cell area is achieved with a two-finger transistor. We also show that for a range of W FET , the cell area is limited by the metal pitch of bit- and source-lines. As a result, in the metal pitch limited (MPL) region, W FET can be increased with no change in the cell area. We analyze the impact of increase in W FET in the MPL region on the write margin and cell tunneling magneto-resistance (CTMR) of different genres of STT MRAMs. We consider conventional STT MRAM cells in the standard and reverse-connected configurations and STT MRAMs with tilted magnetic anisotropy for the analysis. By increasing W FET from the minimum to the maximum value in the MPL region (at iso-cell area) and reducing read voltage to achieve iso-read disturb margin, 2X improvement in write margin and 27% improvement in CTMR is achieved for the reverse-connected STT MRAM. Similar trends are observed for other STT MRAM cells.