On error modeling of electrical bugs for post-silicon timing validation

There is great demand for an accurate and scalable metric to evaluate the functional stimuli, testbench checkers, and DfD (Design-for-Debug) structures used in post-silicon timing validation. In this paper, we show the inadequacy of existing methods (due to either inaccuracy or a lack of scalability...

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Hauptverfasser: Ming Gao, Lisherness, P., Kwang-Ting Cheng, Jing-Jia Liou
Format: Tagungsbericht
Sprache:eng
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