A 1.2-V 250-MS/s 8-bit pipelined ADC in 0.13-µm CMOS

This paper describes the implementation and experimental results of a 250 MS/s 8-bit pipelined analog-to-digital converter (ADC) in a 0.13-μm CMOS process. The ADC uses a dedicated sample-and-hold amplifier (SHA) to achieve excellent linearity performances with high SFDR and very flat SNDR. Stage scaling in the pipeline chain is adopted to lower the power consumption. The ADC measures a SFDR of over 60 dB and 7.45 ENOB at 250 Ms/s with an input frequency of 19 MHz. SNDR only drops 1.7dB with input frequency increasing from dc to over 70MHz. Including all analog and digital blocks, the total power dissipation of the ADC is 60mW from a 1.2V power supply. The active area is 800 μm×700 μm.