A 10-bit 400-MS/s 36-mW interleaved ADC

A high-speed interleaved pipelined ADC employs a global track-and-hold (T/H) circuit in front of the ADC to avoid sampling time mismatches between channels. Each sub-channel ADC employs both opamp-and time-sharing techniques to reduce power consumption and silicon area. The proposed ADC has been fab...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	Yen-Chuan Huang, Chin-Yu Lin, Tai-Cheng Lee
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Calibration Capacitance Clocks CMOS integrated circuits CMOS technology Gain interleaved ADC opamp sharing technique pipelined ADC Power demand time sharing technique
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Beschreibung
Zusammenfassung:	A high-speed interleaved pipelined ADC employs a global track-and-hold (T/H) circuit in front of the ADC to avoid sampling time mismatches between channels. Each sub-channel ADC employs both opamp-and time-sharing techniques to reduce power consumption and silicon area. The proposed ADC has been fabricated in a 90-nm digital CMOS technology and occupies 0.38 mm 2 . It operates at 400 MS/s and achieves an SNDR of 53.0 dB while the power consumption is 36 mW including an on-chip reference buffer.
DOI:	10.1109/RFIT.2011.6141797