Logic BIST silicon debug and volume diagnosis methodology
Post silicon speed-path debug and production volume diagnosis for yield learning are critical to meet product time to market demand. In this paper, we present Logic BIST speed-path debug technique and methodology for achieving higher frequency demand. We have developed a methodology for Logic BIST p...
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Format: | Tagungsbericht |
Sprache: | eng |
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Zusammenfassung: | Post silicon speed-path debug and production volume diagnosis for yield learning are critical to meet product time to market demand. In this paper, we present Logic BIST speed-path debug technique and methodology for achieving higher frequency demand. We have developed a methodology for Logic BIST production fail volume diagnosis and presented tester time and memory overhead tradeoffs and optimization for enabling volume diagnosis. Results are presented showing successful isolation of silicon speed-paths on Intel® SOCs. |
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ISSN: | 1089-3539 2378-2250 |
DOI: | 10.1109/TEST.2011.6139147 |