High-Throughput Low-Power LDPC Decoder and Code Design

In this paper, we present a method for creating LDPC codes which are specifically designed to be hardware friendly. Our method involves constraining the cyclic shift values in the base H-matrix to reduce the complexity of the cyclic shift hardware. We show that the decoder hardware implementation fo...

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Bibliographische Detailangaben

Hauptverfasser:	Henige, T., Abu-Surra, S., Pisek, E.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Decoding Delay Hardware Parity check codes Power demand Silicon Throughput
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