High-Throughput Low-Power LDPC Decoder and Code Design

In this paper, we present a method for creating LDPC codes which are specifically designed to be hardware friendly. Our method involves constraining the cyclic shift values in the base H-matrix to reduce the complexity of the cyclic shift hardware. We show that the decoder hardware implementation for these codes has higher throughput and lower power consumption than decoders designed for traditional LDPC codes. We provide results showing that these codes maintain the error rate performance expected of LDPC codes while achieving these throughput and power consumption improvements.