A reconfigurable tree architecture with multistage interconnection network

A reconfigurable tree architecture with multistage interconnection network

A novel approach to the design of a reconfigurable tree architecture is presented. The architecture is implemented with an augmented shuffle-exchange multistage interconnection network and is capable of assuming N distinct binary tree configurations, where N is the number of processing elements (PEs...

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Veröffentlicht in:IEEE transactions on computers 1990-12, Vol.39 (12), p.1481-1485
Hauptverfasser: Biswas, N.N., Srinivas, S.
Format: Artikel
Sprache:eng
Schlagworte:
990200 - Mathematics & Computers
Applied sciences
Arithmetic
Circuit properties
COMPUTER ARCHITECTURE
COMPUTER NETWORKS
DESIGN
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
Fault detection
GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
Iterative methods
Logic arrays
Logic testing
Multiprocessor interconnection networks
PARALLEL PROCESSING
PROGRAMMING
Switches
Switching, multiplexing, switched capacity circuits
Systolic arrays
Very large scale integration
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Beschreibung
Zusammenfassung:A novel approach to the design of a reconfigurable tree architecture is presented. The architecture is implemented with an augmented shuffle-exchange multistage interconnection network and is capable of assuming N distinct binary tree configurations, where N is the number of processing elements (PEs) in the system. The novel features of the architecture include fast switching from one configuration to another, simplified hardware in the PEs and the switching network, and simple routing control.< >
ISSN:0018-9340
1557-9956
DOI:10.1109/12.61069