A 6 bit and a 7 bit 80 MS/s SAR ADC for an IR-UWB receiver

A 6 bit and a 7 bit successive approximation register (SAR) analog-to-digital converter (ADC) with conversion rates of up to 80 MS/s are presented in this paper. They will be used in an impulse-radio ultra-wideband (IR-UWB) receiver. The architecture with a switched-capacitor (SC) digital-to-analog converter (DAC) is applied due to its low power consumption. The 6 bit analog-to-digital converter applies the classic switching algorithm which is extended to 7 bit with a minor change to the analog part of the converter. A new kind of flip-flops is used in the SAR which enables synchronous operation during the conversion phase. The integrated circuit is realized in the 250 nm SiGe BiCMOS technology SGB25V of IHP. The cores of both analog-to-digital converters occupy a chip area of 0.36 × 0.28 mm 2 and consume 5 mA from a 2.6 V supply.