Design optimization of CMOS CDC comparators

Design optimization of CMOS CDC comparators

This paper presents design of CMOS CDC-based comparators with an optimum method to suppress dynamic offset for high-speed flash ADCs. The CDC-based comparators are introduced, analyzed, modeled and optimized. The experiment results have verified the design optimization. Compared to the ADCs with ran...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Mingzhen Wang, Hongxi Xue, Gang Yang, Yingjian Wu
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Capacitance
Inverters
Mathematical model
Quantization
Switches
Threshold voltage
Transistors
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:This paper presents design of CMOS CDC-based comparators with an optimum method to suppress dynamic offset for high-speed flash ADCs. The CDC-based comparators are introduced, analyzed, modeled and optimized. The experiment results have verified the design optimization. Compared to the ADCs with random sizing CDC comparators, the dynamic performance in terms of SNR and SFDR has improved over 30% @ the signal frequency lower than 800MHz and over 140% @ the signal frequency higher than 800MHz.
DOI:10.1109/ICCPS.2011.6092215