Precise exception support for decoupled run-time monitoring architectures

Recently, researchers have proposed decoupled monitoring architectures that utilize parallel hardware such as multi-cores or accelerators to enable fine-grained security and reliability checks with low overheads. However, today's decoupled monitoring architectures lack support for precise exceptions and can only detect an exception after the monitored program completes an erroneous operation. In this paper, we present an architectural mechanism to support precise exceptions in nonspeculative processors with decoupled monitors. Experimental results based on an RTL implementation show that our approach has low area, power, and performance overheads even when applied to simple, in-order processors.