A design of the PLB to AHB bus bridge

A design of the PLB to AHB bus bridge

The study in this paper is to solve the compatibility of the PLB and AHB interface. In our FPGA hardware platform, we use the PowerPC embedded in Xilinx Virtex4 as our CPU, which follows the PLB protocol. As our slave IP cores are all designed with the AHB interface, we need to design a PLB-AHB brid...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Kang Li, Li Lei, Yong Fan, Jiang-Yi Shi, Yue Hao
Format: Tagungsbericht
Sprache:eng
Schlagworte:
AHB
bridge
Bridges
Clocks
Data communication
FPGA prototyping
PLB
Program processors
Protocols
System-on-a-chip
Timing
timing conversion
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Beschreibung
Zusammenfassung:The study in this paper is to solve the compatibility of the PLB and AHB interface. In our FPGA hardware platform, we use the PowerPC embedded in Xilinx Virtex4 as our CPU, which follows the PLB protocol. As our slave IP cores are all designed with the AHB interface, we need to design a PLB-AHB bridge to translate the two protocols. This paper describes in detail the designing of such a bridge, which enables the use of AHB interface IP cores in our PLB bus environment.
DOI:10.1109/ICECC.2011.6067676